Mentor Graphics Corporation (MENT) is a global technology leader in electronic design automation software. Our software tools enable companies around the world to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics in order to deliver better products in the increasingly complex world of chip, board and system design.
We are looking for a highly motivated Staff or Sr. Software Engineer to work in the Static Verification group in the Design, Verification & Test (DVT) Division. You will be part of a high-performing R&D software team responsible for designing and developing the Questa Formal, CDC and Autocheck products. You will be teaming up with a senior group of software engineers contributing to final production level quality of new software features, components and algorithms and to support existing software components.
Our software engineering team is a creative, dynamic and highly productive small team environment. We are looking for motivated, highly capable contributors to help develop advanced functional verification tools.
You will develop software in C++ that applies formal analysis and static verification techniques to ASICs and FPGAs SoC described in System Verilog or VHDL. You must understand how to apply netlist creation, traversal, analysis, simulation and formal technologies to solve problems.